In this paper, we describe a silicon debug flow that uses debug-friendly scan test patterns to improve the efficiency of physical fault isolation of timing failures using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-friendly test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.

90 nm process, debugging, failure analysis, fault isolation, silicon, time-resolved emission systems
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Copyright © 2008 ASM International. All rights reserved.
2008
ASM International
Topics
Semiconductor wafer fabrication Silicon
Issue Section:
Fault Isolation and Testing
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