Abstract

The flash considered for failure analysis in this paper is a non volatile memory with a NOR architecture in the array and a stacked gate for the bit cell. The flash failure was from data gain reported from various stages and at different temperatures after leaving the wafer fabrication. The failure can be single bit failure (SBF) or multiple bit failure (MBF). The FA process is comprised of two steps termed electrical failure analysis (EFA) and physical failure analysis (PFA). This paper discusses the method to differentiate failure modes and the efforts of fault isolation. Micro probing and nano probe characterization were important in the understanding of the failure mechanism. As seen in the EFA/PFA section, the reported SBF/MBF failures were actually due to a defect in the Mux and not at the bit cell.

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