This article describes the use of an optimized electrochemical delineation technique with illumination to clearly delineate the P-N junction on Si in short channel devices. In this process, the samples are exposed to a light source while in an aqueous CuSO4/HF/H2SO4 solution which induces a junction voltage between N- and P- type silicon. The N+/P+ dopant regions become the cathode/anode electrode plates. The treatment is simple and reproducible which makes it a practical method for identifying junction related problems at localized areas on a chip. Examples are provided to show the effectiveness of this technique in identifying (1) junction implant shift, (2) N+/P-well junction leak, (3) partially blocked NLDD implant, and (4) P+/N+ junction in high voltage device.

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