The sample preparation required for a typical backside circuit edit (CE) is a significant barrier for some labs, as it requires specific hardware and considerable operator expertise. There are also instances in which it is not possible to mechanically thin the silicon in the typical fashion. This paper addresses the possibility of backside CE be performed on full-thickness silicon devices and the possibility of skipping off the thinning step, as well as the advantages and disadvantages of this approach. Sample trenches are shown, and trenching optimization experiments are described. The paper addresses the issues of navigation, including IR imaging through full-thickness silicon, and how it depends on the sample doping levels. Finally, it presents data on a novel navigational technique that can be employed to improve targeting accuracy. The paper shows that backside CE on full-thickness silicon devices is possible despite the challenges.

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