As a promising candidate for DRAM scaling beyond 40nm technology, the fin cell transistor (FCT) utilizing p-type poly silicon gate (PPG) was proposed. However FCT makes a lot of bridge failure between word-line and landing-plug poly (LPP) connecting source and drain regions in a cell transistor. But this bridge point is so insignificant that the failure was hardly detected by existing read modify write (RMW) pattern. We analyzed this failure with a particular test method. It mostly has been observed to single and odd parity address. We found out that when adjacent gate is active for reading its cell, only the forward bias can run into the LPP with n-type poly-silicon, and low status data would be taken high level turn unlike recess cell array transistor utilizing n-type poly silicon gate (RCAT-NPG) which both high and low status would be reversed.