Abstract

The analyzed new Application Specific Integrated Circuit (ASIC) design failed latch-up test on two input pins during current stress. In order to determine the root cause, the Failure Analysis (FA) with use of backside Emission Microscopy (EMMI) was performed. The EMMI results were followed by detailed layout and circuit analysis. It was found that the root cause of the latch-up is an abutment of two specific cells (called “cell C” and “cell D”), where the N-well was grounded creating a parasitic NPN transistor sustaining the latch-up. A detailed calculation of parasitic interconnection resistances from the layout revealed some differences between latching and non-latching pins. The analytical model to explain the latch-up behavior based on parasitic resistances was applied successfully to root cause analysis. Summarizing, the latch–up behavior can be explained by the abutment of cells C and D, parasitic interconnect resistances and cell location with respect to the substrate bumps. In conclusions the following recommendations were made: 1. Remove the n-well in cell D; 2. Connect specific cells (B and D) to higher supply voltage; 3. Implement p+ guard rings for cells C and D; 4. Optimize placement of ground bumps; 5. Eliminate abutment of cell C and D.

This content is only available as a PDF.
You do not currently have access to this content.