As feature sizes are shrinking beyond 130nm, fresh subsets of failures are coming to light. Multiple site defect analysis with adjacent block comparisons and multiple site comparative nanoprobing have become mandatory for these extraordinary and non-visible defects. There are instances where inspection or analysis will be required at multiple sites over a wide area on a sample. Traditional mechanical deprocessing techniques do not allow us to maintain planarity over a relatively large area, typically tens of microns. This article presents a 'masking technique' that addresses the issue of 'adjusting' the level at several local sites on a microchip. This technique can be utilized at all deprocessing levels of defect analysis and comparative circuit analysis and is time, tools, and labor efficient. Additionally, it enables multiple site nanoprobing, a preferred and essential tool for electrical validation of non-visible failures at technologies 90nm and beyond.