Abstract

The ability to edit a circuit in silicon quickly and confidently is extremely valuable as it permits verification of changes or fixes without the need to generate new reticles and fabricate new silicon. However, dramatic changes in the material used in IC’s combined with the downward scaling of dimensions required the development of a scalable process not only in three dimensions but also in material. Details of this process and results are presented in this paper.

This content is only available as a PDF.
You do not currently have access to this content.