Abstract
This article describes a 90nm technology SRAM soft fail analysis. The bitmaps of affected wafers show a large number of wafer edge dies failing with single cell cluster fails at supply voltages below 1.0V. The fails appear in characteristic areas within a 256k dualport SRAM memory block. Nanoprobing was used for electrical localization at the cell level by means of a Multiprobe atomic force probe (AFP) system. Fail areas exhibit very weak PFET drain currents several orders of magnitude below the target values, while the drain currents of NFET cell transistors are in the expected range. For fail visualization a junction stain was applied to TEM samples to delineate areas with different doping levels. Due to differences in etch behavior between failed and reference areas, missing LDD extensions and a partially blocked source/drain (S/D) implantation were identified as the root cause of the fails.
