The semiconductor industry is recognizing an increasing need to define the compatibility of various products joined in package-on-package configuration by solder reflow. Within the scope of the application, this paper discusses: sample preparation; warpage data collection methods; extraction of usable images and numerical data from the measurements; creation of visual warpage patterns for the top and bottom components of stacked package sets; mathematical determination of variation or separation of parts at critical locations during reflow; and finite element analysis of parts and processes to understand and predict reactions to design changes.

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