Abstract

Shallow junction formation in silicon chips is a hot topic in the semiconductor industry. Reduction of power consumption of integrated circuits and an increase of the device performance would drastically reduce the sizes of circuits and, therefore, would necessitate a similar reduction for the depth of the p-n junctions. This paper performed the flash lamp annealing process application, applied to the CMOS as alternative method to attain the goal of shallow junction in the case. A marginal thermal budget mismatch related failure mode was revealed and explained.

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