Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.

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