Improving semiconductor yield is a multi-dimensional process that must include design, fabrication, and test aspects. Incorporating design-for-manufacturability (DFM) concepts needs to include prior and ongoing learning and experience on what worked and what did not. As feature sizes shrink beyond 130nm, it is possible to identify another class of failures that is more systematic and related not to manufacturing defects but to DFM marginalities related to layout. In this article, it is shown that DFM can also help reduce design sensitivity to process variations. Examples of these failure modes and the lessons learnt are listed: relaxed design rules for repeated patterns, relaxing design rules to reduce yield loss, and special considerations for analog circuit layout.