Indirect electrostatic discharge stressing of a chip with multiple isolated power domains was analyzed. The stress penetrates to the victim domain via common nets having nonnegligible complex impedance and via coupling of the interdomain parasitic capacitors and in some cases may cause chip damage.

capacitors, electrostatic discharge, failure analysis, power isolation, VLSI chips
This content is only available as a PDF.
Copyright © 2006 ASM International. All rights reserved.
2006
ASM International
Topics
Semiconductor wafer fabrication
Issue Section:
Advanced Techniques
You do not currently have access to this content.