Abstract
An aggressive yield improvement program that was undertaken by the engineering teams has culminated in the works reported in this paper. The power down current (Idd_Pd) was one of the major failure modes recorded for CMOS ICs. In essence, any improvement made on the Idd_Pd test yield will result in substantial gain in terms of cost and production capacity. A taskforce to resolve high fallouts for the Idd_Pd was then formed back in the year 2004. This taskforce comprised of members from various engineering teams, for instance, Manufacturing, IC Design, Materials and Failure Analysis (FA). The length of investigation to resolve the complex high Idd_Pd failures had spanned over a period of a year. The team had devised a comprehensive sets of DOEs (Design of Experiments) which were conducted at various contract manufacturing facilities where the ICs were packaged. Results obtained from these DOEs had conclusively pointed to molded materials as the major factor contributing to high Idd_Pd yield loss. Armed with this vital information, FA had performed an indepth electrical diagnosis as well as physical analysis on the molded materials. The analysis results had confirmed contamination of the molding materials by conductive carbonized resin as the cause of high leakage current in ICs. Likewise, the material supplier had found minute contamination in the resin melt. In essence, Idd_Pds that were measured in the range of tens of microamps to thousands of microamps in ICs could be largely attributed to leakages caused by carbonized resin in the molded materials.
