Front side mechanical polishing of integrated circuits poses several technological complexities. This paper describes a unique automatic front side polishing technique, based on polishing at a shallow angle and exposing several layers, for NMOS/PMOS devices. This polishing technique is based on polishing at a very shallow angle up to 0.50 with plus or minus 0.1 micrometer accuracy to the target exposing several layers. The paper provides information on the several steps in the delayering process, namely deprocesing, chemical etching, and physical analysis. The benefits of the automatic polishing method developed are: exposing several metal layers without the need to deprocess to each layer separately, thus reducing both the polishing and the analysis time; the polishing can be stopped at any specific layer; direct and simultaneous measurements of structure overlays; direct inspection of embedded defects; and reducing artifacts associated with the etching process such as oxide steps, over etch, differential etching.