Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. While regular raster and special cache patterns (i.e. weak-write test mode) detect many stuck-at faults, a parametric analysis is needed to identify which defect mechanism is the cause of a cache failure. Pico-probing is the most common method of parametric analysis on SRAM cells, but is becoming increasingly difficult on smaller geometries. These curves can also be taken non-destructively by muxing any bitline (BL) and bitline_bar (BL#) of an internal cache to an I/O pin and sweeping these pins with an external PMU (a test mode known as low yield analysis, or LYA). Unfortunately, a growing amount of leakage on each new process is distorting these LYA testmode I-V curves, making it increasingly difficult to find and differentiate defects. The goal of this paper is to discuss the simulation and silicon results of a concept On-Die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.

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