The power supply transient/quiescent signal (IDDT/IDDQ) methods that we propose for defect localization analyze regional signal variations introduced by defects at a set of power supply ports on the chip under test (CUT). The methods are based on the comparison of the CUT with a golden reference chip, either simulated or determined to be defect-free, with the objective of distinguishing anomalous signal behavior introduced by a defect from that introduced by process variations. However, variations in contact resistance between the probe card and the CUT introduces anomalies in the measured power supply signals that complicates the task of comparing data between chips. This paper presents hardware results that demonstrate the effectiveness of a previously developed calibration technique designed to eliminate these types of signal anomalies introduced by the testing environment. The CUT hardware data presented in this work is calibrated using simulations of the CUT’s power grid and special on-chip sources of stimuli called ‘calibration circuits’. Several novel Look-Up Table based defect localization techniques are proposed that analyze the calibrated power supplies signals. The results of predicting the locations of emulated defects in nine copies of a test chip demonstrate the effectiveness of the techniques.

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