During the wafer-sort stage, critical electrical data on the IC chip performance is collected. As technology advances, smaller geometries are continuously implemented to the production line and, as a result, there may be some issues that are difficult to detect and eliminate at the typical wafer-sort or final-test techniques. This paper presents two successful applications of innovative wafer-sort techniques to solve some difficult issues. In the first case, voltage-stress is implemented in the wafer-sort to draw out yield issues which otherwise go undetected. This additional test component helps to screen-out marginal dies and analyze the post-stress spatial pattern. By applying the MERCAD detection system to localize the fault area and the appropriate delayer techniques, metal microbridge is found. In the second case, wafer-sort collects the testing information for the failing scan chains. This information is mapped to the netlist, schematic, and design layout of the chip. Given this information, together with the design layout, the authors are able to narrow down these issues to some metal pattern defects.

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