IC manufacturers, among other things, have to define a global failure analysis (FA) strategy that is best adopted to the challenges associated to the introduction of the 90 and 65 nm CMOS technologies. This article reviews the existing FA techniques and then describes an FA strategy that is aiming at fast, efficient, and economic learning in the latest 120-65 nm CMOS technologies. The strategy is based on a well-balanced mix and usage of in-line defectivity data, voltage contrast analyses, SRAM bitmap analysis results, OBIRCH fault isolation, and various advanced physical characterization techniques. A SRAM bitmap strategy has demonstrated to be very effective in driving most relevant process improvements, and also OBIRCH applied to parametric test structures has helped significantly in identifying major yield detractors.

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