This paper will demonstrate a new copper (Cu) electroplating technique [1] for accurately isolating high resistance fault locations with resistance below K-order ohms. This phenomenon is achieved by having different electric field intensity leading to different copper deposition rate on the sample surface. From experiments, the interface between the thicker electroplated and thinner electroplated copper layer on the sample surface accurately indicates the high resistance fault location. Also, Optical Microscope (OM) and Focused Ion Beam (FIB) are used to inspect the localized fault site of the electroplated sample. Furthermore, this technique, Electro-Plating Localization Method (EPLM), can process several samples or the entire wafer at the same time. In addition, this technique can be applied in the fully open cases of test vehicles with logical circuit as voltage contrast localization method.

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