This paper describes case histories of 0.13 um bulk CMOS technology analyses using Time Resolved Light Emission (TRLEM). Using this technique, scan chain, timing, and logic failures are shown to be quickly and decisively identified thereby meeting the need for rapid feedback on 1st silicon failures and process excursions.

CMOS, failure analysis, scan chain, silicon, time resolved light emission
This content is only available as a PDF.
Copyright © 2004 ASM International. All rights reserved.
2004
ASM International
Topics
Semiconductor wafer fabrication Silicon
Issue Section:
Optical Techniques
You do not currently have access to this content.