Timing Analysis of a Microprocessor PLL Using High Quantum Efficiency Superconducting Single Photon Detector (SSPD)

This paper describes the analysis of a Phase-Locked Loop (PLL) internal phase detection circuit built in IBM’s 0.13 µm Silicon On Insulator (SOI) CMOS technology by using the Picosecond Imaging Circuit Analysis (PICA) [1,2] tool equipped with the high quantum efficiency Superconducting Single-Photon Detector (SSPD) [3,4]. Signals corresponding to the internal nodes of the PLL are for the first time measured and compared to circuit simulations in order to characterize the behavior of the different components of the circuit.