Process options of FIB circuit edit accessing active area in silicon through chip backside are presented. The full process is divided in modules. The technological readiness of the different modules is discussed. New results for the two most critical modules, endpoint detection of the global FIB trench in silicon, and contact resistivity of FIB deposited metal interconnect on diffusion, are presented. Investigated endpoint detection processes are FIB image contrast of the wells and of STI (shallow trench isolation). The contact to diffusion is in the range of 2-5 x 10-7 Ωcm2 on highly doped n-Si, about 10x higher on highly doped p-Si, with linear I-V characteristic.

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