The introduction of p+ implanted areas at the drain side of source-drain-gate salicide-blocked electro-static discharge (ESD) protection diodes resulted in a better ESD robustness, however at the expense of increased leakage currents in up to 40% of the 90nm technology test structures. Leaky devices are found to be randomly distributed across a wafer. The leakage current exhibits only weak temperature dependence and is linearly increasing with the p-implanted area. Photoemission microscopy revealed spots located exclusively in the p+ implanted areas. TEM imaging visualized, that the leakage path is caused by dislocations, reaching from the silicon surface through the p+n junction zone into the substrate. Based on these results and the implant conditions, a theory of dislocation formation was postulated and countermeasures had been defined.