Abstract

In this paper, Failure Analysis (FA) challenges, reliability issues, and new failure modes for copper technology will be presented. Deprocessing techniques for copper technology have been developed and will be discussed. Front side and backside FA deprocessing techniques for copper layers and low k inter-level dielectric (ILD) layers including: reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and a combination of these techniques will be discussed. In addition, novel gate level deprocessing techniques will be presented.

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