The semiconductor industry’s efforts to integrate dielectrics into Si devices has driven characterization efforts to address the challenges presented by adoption of this new class of materials. Abundant literature exists on the considerations required for CMP process recommendations for successful fabrication, adhesion requirements for both fabrication and assembly, and considerations for interconnect structure to enable wire-bonding. There is also interest in understanding the wafer level test challenges presented by the low-K devices. In addition to the typical concerns about reaching the best compromise of good contact resistance (CRES) performance with a minimum amount of probe damage, low-K materials present an increased risk of compromising the dielectric or barrier layers beneath bond pads. For a better understanding of the dynamic contact phenomenon of probing and its effect on the integrated circuit (IC) metal stack, a specialized in-situ nanomanipulator tool was developed for simultaneous visualization of probing events with data recording of electrical and load measurements. This paper describes initial research with this new tool.