A novel failure analysis approach has been developed to isolate and characterize deep sub micron defects in P<100>- silicon lattice. This technique utilizes unique wet chemical deprocessing and side wall cleaning in conjunction with focused ion beam milling to isolate a single vertical failing DMOS source contact from a parallel array of 462K contacts covered with oxide dielectric and top metal layers. The two methods of analysis and root cause of crystalline lattice dislocation in a vertical DMOS transistor are discussed. TEM examination of implanted dopant interface was carried out in order to determine the nature and origin of lattice dislocations. A study1 indicates that lattice dislocations are generated by deep boron and arsenic implants that are not adequately annealed. In our analysis, these dislocations were observed as loop pairs causing low-level leakage that did not initially allow the part to fail. However, these silicon lattice dislocations do pose reliability issues.