Abstract

The use of time resolved photon emission (TRPE) to compare internal measurements with simulations can dramatically reduce the time required for IC analysis. During debug, this technique makes it possible to probe only transistors of interest. Two limitations must be overcome: precise location of transistor photon emission areas and distinction between photons emitted by closely spaced transistors. Otherwise results may be seriously biased. Introducing CAD auto-channeling for TRPE makes it possible to generate virtual layers where emissions are expected. As a result, transistor TRPE areas can be automatically located and emission from nearby transistors is taken into account, thus significantly reducing the duration of IC analysis.

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