Abstract

With increasing density of metal interconnects and shrinking device sizes with each process generation, there has been a growing interest in the Flash failure analysis (FA) community to approach the devices from the backside. Looking at the process layers like Tunnel Oxide, Poly 1 (floating gate), Oxide Nitride Oxide (ONO) and Poly 2 (control gate) from the backside provides useful information about failure location, failure type and failure mechanism which may be obscure from the front side. This work describes a novel combination of mechanical polishes and chemical etches to delayer Intel’s Flash memory devices from the backside to enable viewing of the bottom of the previously mentioned process layers. In addition to Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) has been attempted to gather more information about the surface details. This technique has been used successfully on Intel’s latest 90 nm flash process and has been verified on earlier process generations.

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