Abstract

The correlation between electrical characteristics and failure modes in some common cases of ESD protection circuitry is described. The investigation is based on experimental results obtained during the qualification of highly integrated CPUs and chipsets manufactured by 0.18 µm CMOS technology. The implementation of these data during qualification of 0.13 µm CMOS products allowed the decrease of qualification throughput time (TPT), and, in some cases, reduction of FA efforts. Some process related and designs related ESD concerns are discussed herein.

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