Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps

SRAM bit fail maps (BFM) are routinely collected during earlier phases of yield ramping, providing a rich source of information for IC failure and deformation learning. In this paper, we present an automated approach to analyzing BFM data efficiently. We also demonstrate the usability of our analysis framework using real BFM test data from a large, modern SRAM test vehicle.