Abstract
This paper proposes a taxonomy of process-induced deformations of IC structures. Such a taxonomy is envisioned as a foundation for yield modeling and development of test strategies, as well as, for design of ICs with redundancy. It is proposed to address the rapidly growing complexity of interaction between process-induced deformations of IC structures and steadily shrinking geometry of deep submicron ICs.
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Copyright © 2003 ASM International. All rights reserved.
2003
ASM International
Issue Section:
Test
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