This article presents a case study to solve an IDDQ leakage problem using a variety of failure analysis techniques on a product. The product is fabricated using a 3-metal-layer 0.25 jam CMOS process with the addition of Matrix's proprietary 3-D memory layers. The failure analysis used both top and backside analytical techniques, including liquid crystal, photon emission microscopy from both front and back, dual-beam focused ion beam cross-sectioning, field emission scanning electron microscopy imaging, parallel-lap/passive voltage contrast, microprobing of parallel-lapped samples, and scanning capacitance microscopy. The article discusses how the application of each of the techniques narrowed down the search for this IDDQ leakage path. This leakage path was eliminated using the two corrective actions: The resist is pre-treated prior to ion implantation to produce a consistent resist sidewall profile; and the Nwell boundaries were adjusted in the next Nwell mask revision.

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