In this paper we discuss the use of Emission Microscopy (EMMI) to examine the events leading to latchup for various Input/Output (I/O) pins of a test chip in order to study the factors that impact latchup sensitivity of VLSI chips. The goal of our study is to identify and characterize the structures that are most prone to latchup in test chips, thus providing countermeasures to be used to improve the overall latchup resistance of commercial chips. As it has been shown in literature [1-3], EMMI can be used to localize areas that are latching up. Here we focus our attention on electrostatic discharge (ESD) into I/O pins, which may lead to latchup inside I/O circuits or in their proximity.

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