Abstract

Application of the high resolution of Transmission Electron Microscopy (HRTEM) plays a very important role in structural analysis and materials characterization for process evaluation and failure analysis in the Integrated Circuit (IC) industry. We summarize TEM observation experience of the common memory failures of a BEST deep trench cell with an N-MOS gate used in CMOS DRAM technology. Memory cell failures are categorized into three areas for discussion – the deep trench (DT) capacitor, the transfer gate (GC), and the borderless bit-line contact (CB) between a transistor and a bit line. Typical examples that occurred in these three areas are presented and provide a basic understanding of normal DRAM cell failures.

This content is only available as a PDF.
You do not currently have access to this content.