The pursuit of shorter and narrower channel transistor processes, especially those employing Shallow Trench Isolation (STI), can readily produce devices that are increasingly susceptible to the formation of sub-threshold, leakage-generating defects. Specifically, STI N-channel devices exhibiting lengths at or below 0.35 um and with widths below 1 um, are at a heightened risk of developing a channel micro-twin defect “pipe” due to the very high compressive stress within the silicon lattice. Wider, sub-0.35 um devices can also exhibit the problem if their channels are in extremely close proximity to an active/STI corner region. Modification of the relevant process parameters can significantly alleviate this stress and reduce the frequency of “pipe” formation.

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