Driving Baseline Yields on ASICs Using Logic Mapping

Logic mapping is the process of automatically correlating inline inspection defects with diagnosed faults from electrical testing. This paper presents a software based tool for this purpose and focuses on its specific use for impacting baseline yield enhancement. A detailed approach to utilizing logic mapping for this purpose is also presented. Results from a 10 wafer study using this tool are analyzed and show a defect correlation success rate of 31%. Additional work is presented for improving the logic mapping success rate and diagnosability of failures.