Abstract

Defect analysis and reduction is a focus in all wafer fabs, but there are many approaches to minimizing defect related yield losses. This paper describes the analysis for defect learning and our methodology for defect reduction within our manufacturing line including wafer selection, optimum allocation of engineering resources, details of the learning process, and objectives (both short and long term) of the defect analysis. The focus of the paper is on our 140nm DRAM technology products.

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