In accordance with the predictions of the International Semiconductor Association, a further decrease in the structural widths of semiconductor devices is expected. For an in-depth characterization of actual structural details, the transmission electron microscopy (TEM)-technique is becoming more and more significant. An urgent requirement is in the visualization of dimensions of the doped regions and estimation of p-n-junctions profile with a high level spatial resolution. The off-axis electron holography, a special TEM-technique, is able to visualize electrically active areas in semiconductors. This article describes a way to achieve sample preparation for TEM-holography from actual memory products and also provides an idea of the potential of this technique for semiconductor failure analysis. It shows that different types and sizes of FET's and testing structures could be visualized by focusing on the physical basics, technical solutions, and sample preparation.