Effect of Corner Underfill Voids on Chip Scale Package (CSP) Performance Under Mechanical Loading

The critical impact of corner voids on the anticipated reliability of CSP subjected to mechanical stresses is demonstrated in this paper. Experimental and numerical simulation results indicate that the presence of a corner underfill void subjects the solder joint to stress values approaching that of a non-underfilled CSP. In the absence of underfill voids, the reliability in drop testing improved when the CSP was underfilled, and the improvement was inversely proportional to the modulus of the underfill in the range studied. Results indicate that underfill quality could potentially play a critical role in determining reliability in the field for products subjected to mechanical loading.