Abstract

This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical transistor concept two gates are used to access one storage cell, which creates a challenge for the analysis of gate oxide fails. A gate oxide breakdown is determined and localized in the memory array by electrical probing and photoemission microscopy. The preparation technique combines focused ion beam (FIB) milling and selective wet chemical etching to expose both gates of the transistor simultaneously. Gate oxide pinholes are decorated by the wet etch to allow efficient inspection in a secondary electron microscope (SEM).

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