Abstract

Smaller technologies and increasing chip functionality has resulted in tightly packed devices and more stacked metal layers. For technologies between 0.25µm and 0.14 µm, stacking packed metal layers required the combination of Tungsten plugs as interconnection and the utilization of Chemical Mechanical Polishing (CMP). “Pillar”, however, is a small metal line, which allows interlevel connections between Tungsten plugs. The size and shape of the pillar can be a yield limiting issue. The process of identification and resolution of the missing metal pillar included yield analysis, electrical and physical failure analysis, root cause analysis and the engineering coordination of photo engineering, etch process engineering, CMP engineering, integration engineering, and inline inspection. Resolving the missing pillar issue has proven to have significant contribution to yield.

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