Abstract

For its latest generation of high performance logic applications, Motorola employs a 0.13 µm CMOS technology with shallow trench isolation (STI). The contact dimension and spacing requirements for the dense areas of the circuitry, such as the cache, are quite aggressive. We recently encountered single bit and massive array failures, which were traced to an electrical short between tungsten contacts. We report here the failure analysis, which involved electrical and physical testing techniques.

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