Multi chip packages provide higher functionality in a module using multiplicity of dice. One specific packaging technology known as Stacked Chip-Scale Packaging raises new challenges for the failure analysis community. A methodology to perform full electrical isolation and failure analysis without damaging the electrical connectivity on either package or any of the dies in a stacked 2-die package is described. A second challenge is to obtain analysis result in a limited time frame in order to improve manufacturing yield and perform corrective action effectively. Example of successful failure analysis following this methodology on units with failure in packaging unit and units in failure in the die are presented.