Abstract

The use of analog blocks in deep submicron intergrated circuits has become commonplace. The process used for these circuits is tuned for pure digital applications. Thus, identification of failures in these blocks requires a detailed understanding of the design, test, and process not previously done with digital failure analysis. This paper will detail the method, results, and solution to a silicided related integral non-linearity in a deep submicron 10-bit DAC.

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