Achieving high yield in manufacturing of the ICs requires optimization of the processes to provide sufficient process margins affording small deviation from the optimal processing conditions without yield loss. This paper demonstrates the optimization of the process for the improved product yield. Substantial yield loss has been observed in the product wafers due to excessive soft current leakage in the guard ring PtSi Schottky diodes1. Physical failure analysis has determined that these leakages were related to the presence of dislocations in the active device regions and different platinum silicide rich phases including: Pt12Si5, Pt6Si5, Pt2Si and Pt3Si. The desired phase is PtSi. The root cause of these defects was associated with the rapid thermal annealing (RTA) used to form the guard ring PtSi Schottky diode platinum silicide contact. The usage of the furnace annealing reduced the leakage of the guard ring Schottky diodes by eliminating dislocations and the presence of the platinum rich phases of the silicide. A variety of the failure analysis techniques were successfully employed in this work including: (1) curve tracer analysis of the Schottky diodes I-V characteristics combined with the emission microscopy of the diodes with consecutive deprocessing of the top metal layers for the purpose of avoiding usage of the back side emission microscopy; (2) scanning electron microscopy (SEM) of the Wright etched cross-sections to determine presence of defects in active device regions, (3) transmission electron microscopy imaging and electron diffraction of the diode cross-sections for determination of the nature of the defects and the structure of the phases present; (4) synchrotron x-ray section topography for determination of the some of the dislocations origins.