The continuous scaling of memory technology drives, among other things, an increasing vertical integration. The storage capacitor of a memory cell can be formed as a deep trench into the Silicon to allow high capacitance with a minimum footprint. This paper summarizes preparation techniques especially developed for vertical dielectrics, which are used, for example for the deep trench storage capacitor and the vertical access transistor for this capacitor. The preparation methods employ mechanical polishing, focused ion beam milling and chemical etching to allow for some of the best possible inspection in SEMs and TEMs.

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