Abstract

In this report our SRAM failure analysis flow based on a two metal SRAM and a six transistor cell design is presented. The basic SRAM failures inside the cell array are considered. With standard SRAM tests, the failing cells are detected and a fail bitmap with the physical location of the failing cells is generated. The SRAM failures are classified by the pattern formation of the fail cells. The main focus is on the analysis of single bit failures. In contrast to the often limited physical preparation of SRAMs, a detailed description of the electrical analysis with microprobes, especially of single bit cells, is given. The electrical cell analysis is not limited to hard fails. Soft fails are also accessible. For the different failure classes of the flow, a detailed description of the preparation and physical localization methods e.g. voltage contrast and electrical characterization methods using microprobes is given. Furthermore, analysis results are presented for the different failure classes.

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