Abstract

In this paper, we introduce an example of successful failure analysis using combination of several fault localization techniques on a 0.18 um CMOS device. These techniques contain both front and backside localization techniques. Front side techniques are the following: emission microscopy, liquid crystal analysis, and electron beam (e-beam) probing with focused ion beam (FIB) milling. The backside techniques are optical beam induced current (OBIC) and optical beam induced resistance change (OBIRCH). We discuss the fault mechanism, including the relation between the “hot” spot of these analyses and the failure location in the circuit.

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